Title:
DEVICE AND METHOD FOR BUS COLLATION TYPE PROCESSING
Document Type and Number:
Japanese Patent JP3175896
Kind Code:
B2
Abstract:
PURPOSE: To provide a bus collation type processor for realizing failsafe collation by using normal non-failsafe collation logic without using special failsafe collation logic in a bus collation logic circuit.
CONSTITUTION: This processor is constituted of a timer for activating an intermittent diagnostic processing, two duplex processors 11a and 11b activated by the timer for supplying test data strings including non-coincident data onto a bus and a diagnosis control circuit 18 for monitoring the response of the bus collation logic circuit 12 to the test data and outputting judgement output inverted for respective intermittent diagnostic processing cycles when the response indicates an operation stipulated beforehand. Thus, the degradation of processing performance which is a fault in the case of turning the bus collation logic circuit to failsafe is prevented, collation logic is simplified, the processor is miniaturized by the simplification and reliability is improved.
Inventors:
Makoto Nomi
Masaru Takaoka
Nobuyasu Kanagawa
Kobayashi Nobuhisa
Masaru Takaoka
Nobuyasu Kanagawa
Kobayashi Nobuhisa
Application Number:
JP9424994A
Publication Date:
June 11, 2001
Filing Date:
May 06, 1994
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G06F11/08; G05B9/00; G06F11/18; G06F11/22; (IPC1-7): G06F11/18
Domestic Patent References:
| JP58109944A | ||||
| JP63254537A | ||||
| JP4843240A | ||||
| JP535514A | ||||
| JP2138636A | ||||
| JP452930A | ||||
| JP6168150A |
Attorney, Agent or Firm:
Yukihiko Takada