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Title:
DEVICE AND METHOD FOR DECIDING PARALLEL POSSIBILITY AND PROGRAM CONVERSION DEVICE USING SAME
Document Type and Number:
Japanese Patent JPH05250341
Kind Code:
A
Abstract:

PURPOSE: To provide the device and method which easily and speedily decide parallel possibility even if there is a conditional branch instruction or subroutine call instruction in a loop or if the suffix of an array are arithmetic expressions and the program conversion device which uses them.

CONSTITUTION: A source program which is inputted from an input means 60 is converted into intermediate codes by an intermediate code generating means 61. Loops, arrays, subroutines, and variables are detected from the intermediate codes by a loop detecting means 62, an array/subroutine detecting means 63, and a variable extracting means 64. Further, a simulating means 66 performs simulation and variables whose values are defined by program statements and information on their positions are registered in a storage means 65. A deciding means 67 checks data reference relation as to variables whose values are referred to by program statements according to the positions where the values are defined to decide the parallel processing possibility.


Inventors:
ZAIKI KOUJI
Application Number:
JP30016592A
Publication Date:
September 28, 1993
Filing Date:
November 10, 1992
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F9/45; G06F9/44; G06F15/16; (IPC1-7): G06F15/16; G06F9/45
Attorney, Agent or Firm:
Nakajima Shiro