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Title:
DEVICE AND METHOD FOR ERROR DETECTION AND SIMULTANEOUS SWITCHING NOISE REDUCTION
Document Type and Number:
Japanese Patent JPH06119197
Kind Code:
A
Abstract:

PURPOSE: To effectively detect an error without increasing effective data bandwidth while reducing noise due to simultaneous switching by coding data signals to be outputted from the output pins of a digital IC chip so that they have equal numbers of 1's and 0's in respective cycles.

CONSTITUTION: This coding constitution is outputted so as to code the output pins of a single end of the digital IC chip, respective coded words have equal numbers of 1's and 0's, and equal numbers of driving currents and sink currents are therefore generated, so that a net signal current of 0 is left. On the decoding side of a receiver, counting is performed so as to determine whether or not the numbers of 1's and 0's are equal. When the number of received 1's and the number of received 0's are equal, none of the coded words has a single bit data transmission error. If there is a difference between those numbers, it is considered that the coded words have the data transmission error.


Inventors:
POORU SHII UEIDO
SAMIYUERU EICHI DANKAN
DONARUDO DABURIYUU SUMERUSAA
Application Number:
JP15130691A
Publication Date:
April 28, 1994
Filing Date:
June 24, 1991
Export Citation:
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Assignee:
DIGITAL EQUIPMENT CORP
International Classes:
G06F11/00; G06F11/10; H03K17/16; H03K19/003; H03M5/14; H03M7/00; H03M7/14; H03M7/20; H03M13/00; H03M13/51; H04L1/00; H04L25/02; (IPC1-7): G06F11/00; H03K17/16; H03K19/003; H03M7/14; H03M13/00; H04L1/00
Attorney, Agent or Firm:
Minoru Nakamura (7 outside)