Title:
DEVICE AND METHOD FOR PHASE DETECTION FOR USE WITH DIGITAL PHASE LOCKED LOOP OR OTHER PHASE SENSITIVE DEVICE
Document Type and Number:
Japanese Patent JPH0738428
Kind Code:
A
Abstract:
PURPOSE: To adjust loop bandwidth and phase by sampling a received data signal with an output signal of a phase-locked loop and generating a phase proceeding signal or a phase delay signal based on the comparison between samples. CONSTITUTION: A phase comparator 18 gives a reference clock signal or an output signal that shows the relative phase of a received data signal f1 , and a phase-locked loop output signal f0 is used to sample the signal f1 . FFs 137 and 139 compare the signal f1 with a DPLL output signal, and when the signal f1 precedes an output signal of the divider 16, the FF 137 sets a signal G to H. Because the FF is directly locked by the f0 , the signal G is set to H in a rise section of f transition. The FF 139 has a signal L set to H each time the f0 transition, and because of 1/2 delay that is generated by the F139, Sfo is set to H after 1/2 cycle passes after the f0 is set to H. In this way, phase correction is performed about positive transition of the signal L.
Inventors:
REBUAIN SUTEIIBUN ENU
Application Number:
JP18801991A
Publication Date:
February 07, 1995
Filing Date:
July 02, 1991
Export Citation:
Assignee:
MOTOROLA INC
International Classes:
H03D13/00; H03K5/00; H03K5/26; H03K5/13; H03K5/22; H03K23/66; H03L7/00; H03L7/06; H03L7/085; H03L7/095; H03L7/099; H04L7/033; (IPC1-7): H03L7/06; H03L7/085
Domestic Patent References:
| JPS5352041A | 1978-05-12 | |||
| JPS56122239A | 1981-09-25 | |||
| JPS53141560A | 1978-12-09 |
Foreign References:
| US4051440A | 1977-09-27 |
Attorney, Agent or Firm:
Shinsuke Onuki (1 person outside)
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