Title:
DEVICE AND METHOD FOR PROCESSING DATA
Document Type and Number:
Japanese Patent JP3599437
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To easily and exactly detect and hold the timing of arbitrary and plural interrupting requests.
SOLUTION: Plural interrupting request signals A-D are latched by correspondent interruption latch registers 1A-1D. By writing a high-level signal into any prescribed one of condition selecting registers 2A-2D, any prescribed one of outputs from the interruption latch registers 1A-1D is outputted through AND circuits 3A-3D to an OR circuit 4. The edge of the signal outputted from the OR circuit 4 to be changed from the low level to the high level is detected by an edge detection circuit 5 and when a pulse generated at detection timing is inputted to a count value holding register 6, the count value holding register 6 holds the count value of a counter 7 at that time.
Inventors:
Yasuyuki Yamamoto
Application Number:
JP20741495A
Publication Date:
December 08, 2004
Filing Date:
July 21, 1995
Export Citation:
Assignee:
株式会社ソニー・コンピュータエンタテインメント
International Classes:
G06F9/48; G06F3/033; G06F3/0346; G06F9/46; (IPC1-7): G06F9/46; A63F13/04; G06F3/033
Domestic Patent References:
| JP6348507A | ||||
| JP2134182A | ||||
| JP7177528A | ||||
| JP8226793A |
Attorney, Agent or Firm:
Masatake Suzuki