To provide a method for performing variable phase bit sampling that minimizes requirements for resynchronization of downstream digital processing in a system incorporating adjustable bit phase sampling.
A sampling device is provided with a sampling circuit, and the sampling circuit is provided with a data input and a clock input. Bit phase sampling uses a variable delay element, and a variable delay circuit supplies an adjustable trigger signal. The trigger signal controls a sampling phase in accordance with a first delay control signal. A fixed delay circuit delays an output signal for a predetermined amount of time in accordance with at least one delay control signal. The variable delay element connects an optional clock stream having the possibility of being latently destroyed only to a data sampling device to be able to utilize a fixed delay session.
THANDAPANI SENTHIL
FINCHER CLINT
| JP2003218847A | 2003-07-31 | |||
| JP2000196571A | 2000-07-14 | |||
| JPH11275066A | 1999-10-08 | |||
| JPS6170831A | 1986-04-11 |