Title:
DEVICE FOR MODELIZING INTEGRATED CHIP PACKAGE AND METHOD FOR OPERATING THE SAME
Document Type and Number:
Japanese Patent JPH07306887
Kind Code:
A
Abstract:
PURPOSE: To allow a computer system to normalize a partial space based on a user parameter, and to modelize and display an integrated chip package by finite element analysis.
CONSTITUTION: A volume generator 2 generates a volume related with each part by using a parameter for normalizing the part of an integrated chip package provided by a parametric processor 1. A mesh generator 4 divides the volume into sufficiently small elements by using a volume coordinate from a computer system 3. A finite element analyzing processor 5 executes the analysis of physical stress or thermal stress to the package by using those elements, and after the analysis is completed, the result is displayed on a display device 6.
Inventors:
DAABIN AARU EDOWAAZU
Application Number:
JP30416694A
Publication Date:
November 21, 1995
Filing Date:
November 01, 1994
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC
International Classes:
G06F17/50; G06T17/20; H01L21/66; H01L23/00; G01R31/26; (IPC1-7): G06F17/50; G01R31/26; H01L21/66; H01L23/00
Attorney, Agent or Firm:
Akira Asamura (3 outside)