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Title:
DEVICE FOR PROGRAMMING PLURAL ARRAY CONTROL SIGNAL LINES BETWEEN MEMORY CONTROLLER AND MEMORY ARRAY
Document Type and Number:
Japanese Patent JPH01260693
Kind Code:
A
Abstract:

PURPOSE: To improve flexibility by providing a program RAM constituted of memory elements arranged in m columns n rows, a programmable partial cycle index register, a sequence control means and a signal MUX means.

CONSTITUTION: The program RAM 20 is divided to m pieces of timing sequence, and timing transition is decided by that a bit exists in the sequence. Further, the RAM 20 contains the programmable partial cycle index register 28 for storing a partial cycle index, and each index answers to one of micro-sequence specified by the RAM 20, and encoding of a bit incorporated in each index specifies specified partial division of a cycle causing the timing transition in them. Then, a sequence controller 24 sequences arrays ranging to the whole access by selecting the column of the RAM 20, and the signal MUX 22 selects memory array control lines 40-48 according to kinds of operation. Thus, different control signal timing are dealt with, and the flexibility is improved.


Inventors:
ATEIKU BAJIYA
ROBAATO DOYUZETSUTO
EMU BUITSUTARU KINI
KENTO MEISON
MAAKU ESU MAIAASU
SANIIRU SHIENOI
Application Number:
JP14842088A
Publication Date:
October 17, 1989
Filing Date:
June 17, 1988
Export Citation:
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Assignee:
INTEL CORP
International Classes:
G11C7/22; G11C11/407; G11C11/401; (IPC1-7): G11C11/34
Attorney, Agent or Firm:
Masaki Yamakawa (2 outside)



 
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