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Title:
DEVICE SIMULATION
Document Type and Number:
Japanese Patent JPH04118959
Kind Code:
A
Abstract:

PURPOSE: To accurately perform two-dimensional device simulation even to a semiconductor circuit having a three-dimensional structure constituted of a plurality of elements by preparing input data by arranging the two-dimensional cross section and wiring of each element constituting the semiconductor circuit of the three-dimensional structure.

CONSTITUTION: Initially, the two-dimensional cross section of each element A-D is segmented. The electrodes of each element segmented in the two-dimensional cross section are classified into a power source, earth electrode, gate electrode, and other electrodes and the electrode to be wired is extracted from the other electrodes. Then the plurality of the segmented elements are arranged in a two-dimensional plane. The electrodes to be wired of the arranged elements are wired with each other in accordance with a mask pattern. When the wiring is completed, whether or not the wires intersect other wires is checked and, when wires 1 and 3 which do not intersect other wires are obtained, the arrangement of the elements and wiring is decided. Then input data are prepared by deciding the coordinates of the elements and wiring and correlation between each section and materials from the mask pattern. Finally, two-dimensional device simulation is performed by using the prepared input data.


Inventors:
KANBARA ITARU
Application Number:
JP23711990A
Publication Date:
April 20, 1992
Filing Date:
September 10, 1990
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L21/822; G06F17/50; H01L27/04; (IPC1-7): G06F15/60; H01L27/04
Attorney, Agent or Firm:
Hidekazu Miyoshi (1 outside)



 
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