PURPOSE: To easily obtain synchronization and to exactly read a digital signal by sending the information of a bit length as a start bit which is sent before the sending of address information from a sensor.

CONSTITUTION: A clock generator 1 is composed of two sets of inverters Inv1, and Inv2, resistances R1 and R2 and a capacitor C1 and a clock output is inputted to an (n+2)-adic counter decoder 2. Then, a high level signal appears successively to output terminals Q0, Q1WQn, Qn+1. Out of the outputs, the outputs of the Q1 and Q3WQn for address setting are sent through an address setting switch 4 and logical sum circuit OR to a receiver as a pulse signal and the Q2 is caused to be an open condition. Then, the pulse output of the Q1 independently appears and when it is used as the start bit, the time width of one bit can be exactly known. Thus, the synchronization can be easily obtained with the receiver and the digital signal can be read.