Title:
DEVICE FOR TRACING EFFECTIVE DIGIT
Document Type and Number:
Japanese Patent JPS5412236
Kind Code:
A
Abstract:
Method and means are described for the tracking of digit significance upon operands arithmetically combined in a series of binary operations such as addition, subtraction, or shifting in a decimal computer. The digits are decimally encoded in a format having enough excess capacity such that nonsignificant digits are unique. As part of the arithmetic combining of the operand, pairs of digits of like order but possibly mismatched as to significance and by observing a predetermined rounding rule may also cause a carry value to be propagated to a digit position of higher order. In subtraction by complement addition, an additional carry is propagated to a higher order position conditioned upon there being either a local overflow, a nonsignificant subtrahend, or a nonsignificant minuend and a subtrahend less than an amount specified by a rounding rule. Between the two operands, this results in the rounding of the more precise operand to the least significant digit position of the less precise operand. The method and means are applicable to floating point, sign plus magnitude, radix and diminished radix complement number representation forms.
Inventors:
GUREN JIYOOJI RANGUDAN JIYUNIA
Application Number:
JP5903078A
Publication Date:
January 29, 1979
Filing Date:
May 19, 1978
Export Citation:
Assignee:
IBM
International Classes:
G06F7/00; G06F7/483; G06F7/38; G06F7/493; G06F7/494; G06F7/50; G06F7/506; (IPC1-7): G06F7/00