Title:
CPUサージ低減および保護のための装置および方法
Document Type and Number:
Japanese Patent JP4101808
Kind Code:
B2
Abstract:
Methods and systems of providing power to a central processing unit (CPU) provide for enhanced surge protection during CPU current consumption going from high current to low current consumption. In one approach, a circuit as a power output stage with an output node, and a controller circuit coupled to the power output stage. The controller circuit selectively switches the power output stage into a current ramp down mode based on detection of a voltage surge at the output node. The power output stage has an associated current ramp down rate. The CPU is coupled to the output node and a surge notification input of the power output stage, where the power output stage accelerates the current ramp down based on a notification signal from the CPU for a duration proportional to the change in CPU current consumption from high to low current consumption.
Inventors:
Nguyen, Don
Alex Weizmann
Alex Weizmann
Application Number:
JP2004565547A
Publication Date:
June 18, 2008
Filing Date:
December 18, 2003
Export Citation:
Assignee:
Intel Corporation
International Classes:
H02M3/155; G06F1/28; G06F1/30; G06F3/00; H02H9/04
Foreign References:
| US6188209 |
Attorney, Agent or Firm:
Tadahiko Ito
Shinsuke Onuki
Tadashige Ito
Osamu Miyazaki
Shinsuke Onuki
Tadashige Ito
Osamu Miyazaki