PURPOSE: To make it possible to realize high speed operation using a small-scale hardware constitution by subtracting values obtained by converting absolute values of a divisor and a dividened to logarithms converting the result to a linear value and adding a code corresponding to input.
CONSTITUTION: Input values held by registers 1, 1' are inputted to uppermost bit judging circuits 2, 2' and the uppermost bit is judged. The output of the uppermost bit judging circuits 2, 2' is inputted to multiplexers 3, 3' in which input values are inputted and decoders 4, 4', and the input values are quantized at quantizing width determined by the uppermost bit, and at the same time, 4-bit code determined by the uppermost bit is outputted, and values converted to logarithms are stored in registers 5, 5'. The output of registers 5, 5' are subtracted by a ALU 6 and the result of subtraction is inputted to a decoder 7, and logarithmic values are converted to linear values and stored in a register 8. On the other hand, the codes of the input values are inputted to a code determining device 9 and determined codes are stored in the code bit of the register 8.
HONMA KOICHI
SATO YOSHIO
