Title:
DIAGNOSIS METHOD FOR LOGICAL UNIT SYSTEM
Document Type and Number:
Japanese Patent JPS5330246
Kind Code:
A
Abstract:
PURPOSE: To secure a high-accuracy diagnosis even in case a collation circuit is not available or a common circuit is available, by having an analyzation of the return data.
Inventors:
KISHI SEISHICHI
OONISHI NOBORU
OOTSU YOSHIKATSU
OOMA TOSHIO
SUZUKI MASANORI
OONISHI NOBORU
OOTSU YOSHIKATSU
OOMA TOSHIO
SUZUKI MASANORI
Application Number:
JP10523576A
Publication Date:
March 22, 1978
Filing Date:
September 02, 1976
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE
FUJITSU LTD
FUJITSU LTD
International Classes:
G06F11/16; G01R31/00; G01R31/28; G06F11/00; G06F15/16; G06F15/177; (IPC1-7): G01R31/00; G01R31/28; G06F11/00; G06F15/16