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Title:
DICING METHOD OF COMPOUND SEMICONDUCTOR WAFER
Document Type and Number:
Japanese Patent JPH04276645
Kind Code:
A
Abstract:

PURPOSE: To make up for a difficult point caused at a scribing method and a blade method which are executed to a dicing line formed on a semiconductor wafer composed of a III-V compound and to obtain a perfect chip without sharply increasing a chip size and by enhancing a material efficiency.

CONSTITUTION: At a semiconductor wafer composed of a III-V compound, dicing lines 4, 5 formed on the semiconductor wafer are diced in a direction perpendicular to an orientation flat at (011) by a scribing method after flaws have been formed and a force has been exerted, and the dicing lines which are parallel to the orientation flat at (011) are diced by a blade method. As a result, chippings are not produced and it is not required to form an excess space on the dicing lines 4, 5. Consequently, a material efficiency is increased, and the title method contributes extremely largely to the semiconductor wafer composed of the expensive III-V compound.


Inventors:
IMAMURA SOICHI
Application Number:
JP6255091A
Publication Date:
October 01, 1992
Filing Date:
March 04, 1991
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
B28D5/00; H01L21/301; H01L21/302; H01S5/02; (IPC1-7): H01L21/78
Domestic Patent References:
JPS62272583A1987-11-26
Attorney, Agent or Firm:
Norio Ohu



 
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