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Title:
DIELECTRIC BREAKDOWN LIFE SIMULATION METHOD, AND SILICON WAFER SURFACE QUALITY EVALUATION METHOD AND PROGRAM
Document Type and Number:
Japanese Patent JP2010062346
Kind Code:
A
Abstract:

To provide a simulation method mathematically and statistically incorporating quality states of a silicon wafer surface into a stochastic process of dielectric breakdown in the evaluation of the reliability of an insulator thin film.

The dielectric breakdown life simulation method of simulating using a computer the insulator thin film formed on a silicon wafer by a Monte Carlo method includes steps of setting dielectric breakdown measuring conditions, setting the distribution of surface faults of the wafer and fault size, mesh-dividing the insulator thin film into cells and convoluting the surface faults into the cells, calculating a reference scale of a time taken until the dielectric breakage occurs in the insulator thin film, simulating the stochastic process of dielectric breakdown of insulator thin films of all capacitors set on the silicon wafer by the Monte Carlo method by using the computer, and statistically processing the dielectric breakage of all the capacitors.


Inventors:
TAKEDA RYUJI
Application Number:
JP2008226714A
Publication Date:
March 18, 2010
Filing Date:
September 04, 2008
Export Citation:
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Assignee:
COVALENT MATERIALS CORP
International Classes:
H01L29/00; H01L21/336; H01L21/822; H01L27/04; H01L29/78; H01L21/316
Attorney, Agent or Firm:
Mitsuyuki Matsuyama
Tetsuma Ikegami
Akira Sudo