DIELECTRIC ISOLATION TYPE SEMICONDUCTOR DEVICE

Japanese Patent JPH08306892

A

PURPOSE: To prevent deflection from being produced without deteriorating withstand voltage performance between semiconductor regions by forming a slot trench in an island shaped device region surface below a high potential wiring, filling an insulator in the insulation slot, and covering the insulation slot with an insulation layer, and further forming a high potential wiring on the insulation layer.

CONSTITUTION: An insulation slot 15 is formed in the surface of an island shaped device region 3 located below a cathode wiring 13 that becomes high potential, and the slot is filled with an insulator. The insulation slot 15 is formed in the lead direction of the cathode wiring 13, and an insulation layer 16 is formed between the insulation slot 15 and the cathode wiring 13 for covering the insulator slot 15. Here, the width of an opening in the insulation slot 15 is more wider than that of the cathode wiring 13. Hereby, even though the thickness of the insulation layer is thin, an insulation distance can be lengthened in a region where the high potential wiring 13 and a low potential semiconductor region intersect, and hence withstand voltage is secured, and further deflection of a dielectric isolation type semiconductor device can be reduced.

KISHIDA TAKASHI
SUZUMURA MASAHIKO
MAEDA MITSUHIDE
HAYAZAKI YOSHIKI
SHIRAI YOSHIFUMI
TAKANO KIMIJI

JP10641495A

November 22, 1996

April 28, 1995

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MATSUSHITA ELECTRIC WORKS LTD

H01L21/762; H01L21/76; H01L27/12; H01L29/78; H01L29/786; H01L29/861; (IPC1-7): H01L27/12; H01L21/762; H01L29/78; H01L29/786; H01L29/861

Shigeji Sato (1 person outside)

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