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Title:
DIFFERENTIAL AMPLIFIER CIRCUIT
Document Type and Number:
Japanese Patent JP3565884
Kind Code:
B2
Abstract:

PURPOSE: To output an output waveform having high voltage gain and reduced in its distortion and to prevent switching speed from being reduced by connecting an output limiting means between an output terminal constituting a complementary output terminal following the current amplification of a complementary output from a differential pair by an output buffer pair and an inverted output terminal.
CONSTITUTION: An input is impressed to an input terminal I1 and an inverted input terminal I2 connected to respective gates of MESFETs 11, 12 constituting a differential pair 1. A complementary output from the differential pair 1 is outputted to the drains of the FETs 11, 12. The outputs are DC-amplified by an output buffer pair 2 consisting of FETs 16, 17 and respectively extracted from an output terminal O1 and an inverted output terminal O2 connected to the drains of FETs 18, 19. The terminals O1, O2 constitutes a complementary output terminal 3 of the pair 2. An output limiting means 4 connected between the output terminals O1, O2 limits the amplitude of the complemantary output from the pair 2. The means 4 consists of an inverted parallel circuit of Schottky diodes 5 and the output amplitude is limited to the forward voltage ΔV (about 0.6V) of the diodes 5, so that the complementary output amplitude is limited to 2×ΔV.


Inventors:
Kubota, Miki
Application Number:
JP1993000302717
Publication Date:
September 15, 2004
Filing Date:
December 02, 1993
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03F3/45; (IPC1-7): H03F3/45
Domestic Patent References:
JP61251216A
JP60182207A
JP4245708A
JP60096009A
JP1124251A
JP62127128U
Attorney, Agent or Firm:
平戸 哲夫
寒川 誠一