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Title:
DIFFERENTIAL AMPLIFIER CIRCUIT
Document Type and Number:
Japanese Patent JPH03163907
Kind Code:
A
Abstract:

PURPOSE: To enable the circuit to code a fine analog signal into a binary signal for amplification by connecting first and second NOR circuits, which are respectively composed of field effect transistors, while being crossed, constituting the amplifier of two inputs and applying bias to the NOR circuit so that input sensitivity can be maximum.

CONSTITUTION: The source electrodes of thin film transistors T2, T3, T5 and T6 are totally connected and this total connecting point is grounded through the drain and source of a thin film transistor T7 for bias supply. A control voltage Va is applied through a terminal 14 to the gate electrode of this thin film transistor T7. For this control voltage Va, the value is set so that the input sensitivity of a differential amplifier circuit can be maximum. To potential difference V of an input signal, positive feedback is loaded through the crossed and connected thin film transistors T3 and T5 and the difference is amplified. Accordingly, an amplification factor is made extremely high especially in an area, where the input potential difference is fine, and as a result, when the potential difference V of the input signal is more than fixed values +VS, -VS, it can be coded into a binary signal without fail.


Inventors:
KANBARA MINORU
Application Number:
JP30380789A
Publication Date:
July 15, 1991
Filing Date:
November 22, 1989
Export Citation:
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Assignee:
CASIO COMPUTER CO LTD
International Classes:
G06G7/12; G11C11/409; H03K5/08; (IPC1-7): G06G7/12; H03K5/08
Domestic Patent References:
JPS5544213A1980-03-28
Attorney, Agent or Firm:
Takehiko Suzue (3 outside)



 
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