Title:
DIFFERENTIAL AMPLIFIER AND ITS PHASE COMPENSATION METHOD
Document Type and Number:
Japanese Patent JP3120763
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a differential amplifier which is capable of reducing parasitic capacitance and operating with higher stability.
SOLUTION: First and second inputs and supplied to first and second FET MP1 and MP2 respectively, and both MP1 and MP2 constitute a 1st differential amplifier pair. Then the first and second inputs are supplied to third and fourth FET MP7 and MP8 respectively, and both the FET MP7 and MP8 constitute a second differential amplifier. With such a constitution, a differential amplifier i.e., a current mirror circuit consisting of FET MN8 and MN7 takes out the output to be supplied to the next stage, only from the drain D of the MP1 or MP8 with regard to the load of both MP1 and MP8.
Inventors:
Naoto Oikawa
Application Number:
JP30913597A
Publication Date:
December 25, 2000
Filing Date:
November 12, 1997
Export Citation:
Assignee:
NEC
International Classes:
H03F3/45; H03F1/08; H03F3/26; (IPC1-7): H03F3/45
Domestic Patent References:
| JP4130807A | ||||
| JP4243308A |
Attorney, Agent or Firm:
Yasuyuki Hata