Title:
差動増幅器
Document Type and Number:
Japanese Patent JP4305472
Kind Code:
B2
Abstract:
An differential LNA has first and second input MOS transistors, with differential inputs applied to their respective control gates and differential outputs taken at their respective drains. The gate-to-drain, Cgd, feedback capacitances of the first and second input MOS transistors are neutralized by respective gate-to-source, Cgs, capacitances in the two neutralizing MOS transistors. A first neutralizing MOS transistor has its control gate coupled to the control gate of the first input MOS transistor, its source node coupled to the drain node of the second input MOS transistor, and its drain node coupled to a fixed potential. A second neutralizing MOS transistor has its control gate coupled to the control gate of the second input MOS transistor, its source node coupled to the drain node of the first input MOS transistor, and its drain node coupled to the same fixed potential. In this manner, similar and opposite potential differences between the gate-and-drain and the drain-and-source regions of the first input MOS transistor are reproduced in gate-and-drain and drain-and-source regions of the first neutralizing MOS transistor. A similar affect is produced in the second input and second neutralizing MOS transistor.
Inventors:
Salem Aid
Gregory Bram
Gregory Bram
Application Number:
JP2006169738A
Publication Date:
July 29, 2009
Filing Date:
June 20, 2006
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
H03F1/14; H03F1/26; H03F3/45
Domestic Patent References:
| JP1105605A | ||||
| JP7297656A | ||||
| JP52095335U | ||||
| JP7015245A | ||||
| JP2004032705A | ||||
| JP62166606A |
Attorney, Agent or Firm:
Masahiko Ueyanagi
Kazuhiko Miyasaka
Kazuhiko Miyasaka