To provide a differential output frequency divider circuit in which a CMOS inverter is used and a delay difference between differential signals does not occur.

The frequency divider circuit for dividing a clock signal to output it is provided with a set input terminal for forcing a signal level of an output signal to be fixed. The differential frequency divider circuit is also provided with: a first frequency divider circuit for forcing the output signal to be fixed by inputting a signal level to the set input terminal; a second frequency divider circuit for forcing the output signal to be fixed by inputting a signal level different from that of the set input terminal of the first frequency divider circuit; and a common-mode detection circuit for inputting the output signals from the first frequency divider circuit and second frequency divider circuit, comparing the signal levels of the output signals, determining whether they are the same, and outputting it to the set input terminal.

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