Title:
デジタルフエーズドアレーのアーキテクチャーと付随する方法
Document Type and Number:
Japanese Patent JP4533572
Kind Code:
B2
Abstract:
Digital phased array architecture and associated method are disclosed that eliminate the necessity of utilizing analog phase shifters in the receive and transmit signal paths. Desired delays are instead generated by adjusting the timing of sampling signals sent to analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) in the receive and transmit signal paths.
Inventors:
Gradi A, Frazier
Application Number:
JP2001566216A
Publication Date:
September 01, 2010
Filing Date:
March 02, 2001
Export Citation:
Assignee:
Raytheon Company
International Classes:
H01Q3/30; H01Q3/26; H01Q3/38
Domestic Patent References:
| JP11330841A | ||||
| JP62175685A |
Attorney, Agent or Firm:
Patent business corporation Odashima patent office