Title:
DIGITAL ACOUSTIC PROCESSING UNIT
Document Type and Number:
Japanese Patent JP3760483
Kind Code:
B2
Abstract:
PURPOSE: To easily build up a digital acoustic system most suitable for the user not sufficiently understanding the clock system.
CONSTITUTION: Plural reception circuits 11-1n provided to an input stage receive input signals DI1-DIn from each digital acoustic equipment. The reception circuits 11-1n detect whether or not a PLL circuit 2 detecting synchronizing clock signals Cks1-Cksn is locked and whether or not the detected synchronizing clock signals CKs1-CKsn are synchronously with a reference clock CK0 and provide an output of flags fL1-fLn and synchronization flags fs1-fsn respectively as the result of detection. A CPU10 references the flags to make discrimination of input disable, processing disable and processing enable as to each digital input signal and displays the result onto a display device 11.
Inventors:
Hirohisa Miyoshi
Tatsuya Umeo
Hiroshi Hamamatsu
Tatsuya Umeo
Hiroshi Hamamatsu
Application Number:
JP17410295A
Publication Date:
March 29, 2006
Filing Date:
June 16, 1995
Export Citation:
Assignee:
Yamaha Corporation
International Classes:
H04S3/00; H04S7/00; (IPC1-7): H04S3/00; H04S7/00
Domestic Patent References:
| JP7086929A | ||||
| JP5244455A | ||||
| JP7147655A | ||||
| JP7121880A |
Foreign References:
| WO1994027234A1 |
Attorney, Agent or Firm:
Masaru Itami