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Patent Searching and Data


Title:
DIGITAL ADJUSTING DEVICE
Document Type and Number:
Japanese Patent JPS56129809
Kind Code:
A
Abstract:

PURPOSE: To simplify the operation and obtain reliable results by a method wherein an alarm signal is outputted only when a continuous period of time during which a factor makes an input signal abnormal by exceeds the specified value.

CONSTITUTION: An input signal (a) is inputted to a detection circuit 2 via an arithmetic circuit 1, and also outputs a signal (b) reducing the bit signal to "1" when an abnormal factor occurs. During a period when the abnormal factor continues to occur, a signal (c) outputted from an OR gate 30 in an alarm circuit 3 is continuously reduced to the signal "1". On the other hand, the output from an inverter 32 is reduced to a signal "1" continuously. Due to signals (c), (d) an up signal from the first pulse generator 33 is sent to an up-down counter 35. In addition, when there is no abnormal factor, a down signal is sent to the counter 35 from the second pulse generator 34. The upper and lower limit values of the count value (q) are set at setting devices 36, 37, while the value (q) is compared with the upper and lower limit values at comparators 38, 39 each, so that an alarm signal AL is generated from FF31 when the (q) is equal to the upper limit value. By so doing, it becomes possible to simplify the operation and obtain reliable results.


Inventors:
NAKAGAWA HIROYUKI
Application Number:
JP3245080A
Publication Date:
October 12, 1981
Filing Date:
March 14, 1980
Export Citation:
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Assignee:
HOKUSHIN ELECTRIC WORKS
International Classes:
G01D1/00; G01D1/04; G01D1/16; G01D1/18; (IPC1-7): G01D1/18
Domestic Patent References:
JPS5087077A1975-07-12