PURPOSE: To obtain an analog data with high accuracy without distortion while adopting simple constitution using a counter circuit by providing a cancelling means so that a pulse width conversion output reduces phase change against the sample period.

CONSTITUTION: A digital data D is fed to a preset input of an up-down counter circuit 3, a frequency 2fs being twice the frequency fs of a sampling clock SC is fed to a load terminal L and the said data D is loaded. On the other hand, an output 7a of the 2nd flip-flop circuit 7 set by the frequency fs of the sampling clock SC and reset by the frequency 2fs having a period 2Δfs being a half of the period fs is fed to an up/down terminal of the up/down counter circuit 3 to select the up or down count of the up/down counter circuit 3. The up/down counter circuit 3 uses a carry pulse C generating a full scale output at count-up and a borrow pulse B generating all '0' at count-down so as to set S or reset R of the 1st flip-flop circuit 4.