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Patent Searching and Data


Title:
DIGITAL-ANALOG CONVERTER
Document Type and Number:
Japanese Patent JPH03235425
Kind Code:
A
Abstract:

PURPOSE: To reduce the current of a current switch while keeping conversion precision, and to realize the low power consumption of a D/A converter by making a low order bit having a margin in the conversion precision into current weighting.

CONSTITUTION: A resistance value in the case an R-2R ladder circuit is seen from a switch S side is 2R/3, and the voltage Vcc-4I.2R/3 of an output terminal OUT at the time when an MSB switch S7 is closed is made to be 1/2 of a full scale, and thus, the voltage Vcc-2I.2R/3 of the output terminal OUT at the time when the next switch S6 is closed becomes 1/4 of the full scale, and the voltage of the output terminal OUT at the time when the switch S5, S4... of an R-2R ladder resistance part is closed becomes 1/8, 1/16... of the full scale. The current weighting reduces a wasteful current, and ineffective power consumption is reduced.


Inventors:
NISHIO SHIGERU
Application Number:
JP3082490A
Publication Date:
October 21, 1991
Filing Date:
February 09, 1990
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03M1/74; H03M1/78; (IPC1-7): H03M1/74; H03M1/78
Attorney, Agent or Firm:
Minoru Aoyagi