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Patent Searching and Data


Title:
DIGITAL CIRCUIT, SEMICONDUCTOR DEVICE, AND CLOCK ADJUSTING METHOD
Document Type and Number:
Japanese Patent JP2007110686
Kind Code:
A
Abstract:

To perform an inspection while compensating for delay variations by automatically adjusting a variable delay circuit using a low-speed versatile inspection apparatus, and to achieve cost reduction and improve inspection quality.

A digital circuit 10a comprising a clock operating circuit for outputting a data signal in accordance with input timing of a clock signal is provided with: variable delay circuits 13-1, 13-2 for giving a predetermined delay time to the clock signal or to the data signal; a delay circuit 14a having a delay time that is a predetermined multiple of a period of a test signal; and a data holding circuit for determining whether delay variation of the data signal is earlier or later than a predetermined time by comparing a time obtained by multiplying the period of the test signal by a predetermined factor with the delay time of the delay circuit 14a, and compensating for the delay time of the variable delay circuits 13-1, 13-2 on the basis of the result of the determination.


Inventors:
YAMAMOTO KAZUHIRO
Application Number:
JP2006238013A
Publication Date:
April 26, 2007
Filing Date:
September 01, 2006
Export Citation:
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Assignee:
ADVANTEST CORP
International Classes:
H03K5/135; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Kihei Watanabe