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Patent Searching and Data


Title:
DIGITAL CIRCUIT SIMULATION METHOD
Document Type and Number:
Japanese Patent JPH04174074
Kind Code:
A
Abstract:

PURPOSE: To realize the operation of a circuit by performing delay simulation on a computer which is used to design a digital circuit so that the logic of a flip-flop is made indeterminate in the case of the input conflict of the flip-flop or when an input spike is lower than a designed value.

CONSTITUTION: For the delay simulation 5 on the computer, circuit connection information 1 containing data on the digital circuit and a test pattern 2 consisting of data on an input and an output expected potential are used. A standard data base 4 is referred to by using a criterion for deciding determinate logic or indeterminate logic according to the time difference of the input conflict of the flip-flop and the time width of the input spike. In a final decision result list 6, the output expected value pattern of a test pattern 6 is compared with the output result pattern of the delay simulation 5 on the computer and when they are all coincident, it is considered that the operation of the circuit is secured. Thus, the operation of the circuit can be secured while it is easily confirmed whether the time difference of the input conflict of the flip-flop and the time width of the input spike meet standards or not.


Inventors:
TAKASUKA YUKISUKE
Application Number:
JP29747290A
Publication Date:
June 22, 1992
Filing Date:
November 02, 1990
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
G06F11/25; G06F11/26; G06F17/50; (IPC1-7): G06F11/26; G06F15/60
Attorney, Agent or Firm:
Shin Uchihara