Title:
DIGITAL CIRCUIT
Document Type and Number:
Japanese Patent JPS62111522
Kind Code:
A
Abstract:
The digital circuit is for receiving a master clock signal at a frequency rate f on an input and delivering a rectangular shaped output signal at a lower frequency (M/N)f where M is an integer and N is an even integer greater than M. The circuit comprises an even number N of series connected flip-flops in a ring arrangement, each flip-flop being connected to receive input signals from the preceding flip-flop and from the following flip-flop and to receive a master clock signal on a clock input. The even numbered flip-flops are of a type different from the type of the odd numbered flip-flops. The outputs of the flip-flops each deliver a rectangular pulse signal having a duty ratio equal to 1/N of that of the master clock signal. The pulse signals are applied to a combination logic of OR type giving an output signal combining the outputs of said plurality of flip-flops.
Inventors:
JIYAN KUROODO KARURATSUKU
Application Number:
JP22347286A
Publication Date:
May 22, 1987
Filing Date:
September 18, 1986
Export Citation:
Assignee:
FRANCE ETAT
TELEDIFFUSION FSE
TELEDIFFUSION FSE
International Classes:
G06F7/68; H03K23/52; H03K3/356; H03K23/00; H03K23/54; H03K23/66; (IPC1-7): H03K23/50
Attorney, Agent or Firm:
Kuro Fukami