Title:
DIGITAL CONTROLLER
Document Type and Number:
Japanese Patent JPH04328601
Kind Code:
A
Abstract:
PURPOSE:To prevent the deterioration of control performance due to a computing time lag by adding together a state feedback signal and a delay compensation signal for production of a control input signal. CONSTITUTION:A computing delay compensation means 20 inputs a digital signal 9 showing the state of a plant and multiplies it by an A matrix 15. Then the means 20 inputs a control input signal held in a holding device 5 and multiplies it by a B matrix 16. Both multiplication results are added together and this addition result is multiplied by a computing time lag T for calculation of a changed variable obtained for the time T of a state vector. Then a state feedback means 12 multiplies the changed variable with the state beedback gain 3. Thus a computing delay compensation signal 18 is obtained. An adder means 14 adds the signal 18 to the signal 8 and outputs a feedback signal 19.
Inventors:
HIROE TAKAHARU
HIRATA DAISAKU
HIRATA DAISAKU
Application Number:
JP9920191A
Publication Date:
November 17, 1992
Filing Date:
April 30, 1991
Export Citation:
Assignee:
MITSUBISHI HEAVY IND LTD
International Classes:
G05B11/36; (IPC1-7): G05B11/36
Attorney, Agent or Firm:
Takehiko Suzue