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Title:
DIGITAL PARALLEL/SERIAL CONVERTER
Document Type and Number:
Japanese Patent JPS648731
Kind Code:
A
Abstract:

PURPOSE: To eliminate the need for idle reading of a data and to avoid duplicated serial processing for a parallel data by transferring the data from the 1st to the 2nd storage means only when a new data is stored in the 1st storage means.

CONSTITUTION: RS-FFs133, 134 and a 4-input AND gate 135 are added. The RS-FF133 is provided corresponding to D-FF 111∼11N. Thus, an empty signal indicating the possibility of entering a new parallel data to the D-FF 111∼11N is outputted from an empty signal output terminal 162. On the other hand, the RS-FF 134 is provided corresponding to the 2nd D-FFs 121∼12N. Thus, a ready signal indicating the possibility to extract a serially processed data is outputted from a ready signal output terminal 143. Moreover, the output of the AND gate 135 is fed to a clock terminal of the D-FFs 121∼12N.


Inventors:
MURAMATSU GOJI
Application Number:
JP16504687A
Publication Date:
January 12, 1989
Filing Date:
June 30, 1987
Export Citation:
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Assignee:
SHARP KK
International Classes:
H03M9/00; (IPC1-7): H03M9/00
Domestic Patent References:
JPS59173839A1984-10-02
Attorney, Agent or Firm:
Fukami Hisaro