PURPOSE: To improve the efficiency of a processor by providing a buffer memory circuit wherein digital data after conversion are written between a data converting circuit and the processor, and by permitting the processor to read the data at need.

CONSTITUTION: For the start of converting operation, a timing generating circuit 16 outputs a counter drive pulse 22 in response to an A/D conversion end signal 25 to drive an input changeover counter circuit 15, and on the basis of the counter value, an input changeover holding circuit 11 selects one of analog inputs to send analog holding output 19. The circuit 16 sends an A/D conversion start signal 24 to an A/D converter 12 a constant time after the output 19. On receiving the A/D conversion end signal 25 from the converter 12, the circuit 16 outputs a write command signal 26 to a buffer memory circuit 13, whose address is specified by an input changeover signal 23, to write A/D- converted digital data 20 in the circuit 13. Simultaneously, the pulse 22 is outputted and the said operation is repeated. A processor 14 reads data 21 at need.