To provide a digital data arithmetic unit that enables minimum testing terminals and a test on a peripheral circuit as an external interface with the same normal signal transmission path and timing by a simple structure.
An arithmetic LSI 16 comprising a serial/parallel conversion part (SP part) 17 for converting input serial data to first parallel data, a digital signal arithmetic part (DSP part) 18 for digitizing the first parallel data to second parallel data, and a parallel/serial conversion part (PS part) 19 for converting given parallel data to serial data and outputting them has a selector part 20 for switching the parallel data given to the parallel/serial conversion part 19 from the second parallel data to the first parallel data in response to a test switch signal input at a test.
JP2002300700A | 2002-10-11 | |||
JP2002358639A | 2002-12-13 | |||
JP2003060813A | 2003-02-28 |
Shigeki Yamada
Junji Kodera
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