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Patent Searching and Data


Title:
DIGITAL DATA CONVERSION METHOD AND COMPRESSION METHOD, DIGITAL ARITHMETIC PROCESSOR AND DIGITAL ELECTRONIC COMPUTER
Document Type and Number:
Japanese Patent JPH11330978
Kind Code:
A
Abstract:

To simultaneously perform addition processings for each digit and to shorten operation time by handling a head binary number, i.e., a combination of signals 'o' showing zeros as a scale of notation for at least one of two digits which are adjacent to each other in any digit among those redundant ternary binary numbers of one or plural digits using 2 as a base.

A ternary register which handles ternary signals uses one of three signals {n, o, p} showing the numeric value {-1, 0, 1} respectively as a signal of a single digit and handles a head binary number, i.e., a combination of signals 'o' showing zeros as a scale of notation not as a partial set of redundant ternary binary numbers for at least one of two digits which are adjacent to each other in any digit among those ternary binary numbers of the or plural digits using 2 as a base. As a result, a head binary number which has no redundancy and uniquely corresponds to a binary number with a small rate of non- zero digits can be set at the center of a scale of notation.


Inventors:
KAWASAKI HIROYUKI
Application Number:
JP13392798A
Publication Date:
November 30, 1999
Filing Date:
May 15, 1998
Export Citation:
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Assignee:
KAWASAKI HIROYUKI
SHINCHI SANGYO KK
International Classes:
H03M5/16; H03M7/30; (IPC1-7): H03M7/30; H03M5/16
Attorney, Agent or Firm:
Tsuruwa Toshio