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Title:
DIGITAL DATA DEMODULATING CIRCUIT
Document Type and Number:
Japanese Patent JPS5864611
Kind Code:
A
Abstract:

PURPOSE: To generate pulses which indicate a rise and a fall of original digital data accurately for modulation of the original ditial data, by setting a reference level in accordance with a reproduction output level.

CONSTITUTION: The output signal (i) of an exclusive OR circuit 16 contains a pulse signal which indicates neither original rises nor falls of digital data. A delay reproduced signal (c), when inputted to two comparators 19a and 19b of a gate signal generating circuit 18, is compared with a plus-side reference level c1 and a minus-side reference level c2, and signals obtained at output sides of the comparators 19a and 19b are inputted to an OR gate 20, so that they cor respond to the peaks of the reproduced signal (c), i.e. original rises and falls of the digital data. For this purpose, the OR gate output (j) is inputted to an AND gate 21 to gate the pulse signal (i), obtaining only a pulse signal K which indicate the original rises and falls of the digital data.


Inventors:
NISHIKAWA YOSHINOBU
Application Number:
JP16450781A
Publication Date:
April 18, 1983
Filing Date:
October 14, 1981
Export Citation:
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Assignee:
SANYO ELECTRIC CO
International Classes:
H03M5/04; G11B20/10; H03M5/12; H04L25/03; (IPC1-7): G11B5/09; H04L25/49; H04L25/493
Attorney, Agent or Firm:
Takuji Nishino



 
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