PURPOSE: To improve the availability of memory capacity and to minimize the omission of image information by storing successively the 1st variable length code data in the order of lower memory addresses and the 2nd variable length code data vice versa and securing the synchronizing between the variable length code data read out from a low address through the center address and the variable length data read out from the highest address through the center address respectively in a reading mode.

CONSTITUTION: A memory 31 of capacity equivalent to two blocks is provided together with a write address generating circuit 36 which outputs the address acquired by a positive or negative count-up operation, a read address generating circuit 40, a register 37 which stores the final address of one of both blocks, and a comparator 38 which compares the data on the other block with the write address stored in the memory 31, the address stored in the register 37, and the center address of the memory 31 respectively.