Title:
ディジタル遅延ライン
Document Type and Number:
Japanese Patent JP4422393
Kind Code:
B2
Abstract:
A digital delay line includes a delay section and a clock providing section. The delay section comprises N (N being a natural number) unit delay elements which are connected in series and each of which is composed of one logic product gate. The clock providing section provides a first clock signal, or a second clock signal having a phase difference of 180° with respect to the first clock signal, to one among the N unit delay elements according to an externally inputted selection signal. The first clock signal is provided to the unit delay elements bearing even numbers, as counted from a clock output terminal, and the second clock signal is provided to the unit delay elements bearing odd numbers. According to the digital delay line, the jitter characteristic of a delay locked loop can be improved, and the area required for designing the digital delay line can be reduced by one-half in comparison to the existing digital delay line.
Inventors:
Raoko
Application Number:
JP2002275213A
Publication Date:
February 24, 2010
Filing Date:
September 20, 2002
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
G06F1/10; H03K5/135; G11C11/407; G11C11/4076; H03H11/26; H03K5/13; H03K5/156; H03L7/081; H03K5/00
Domestic Patent References:
| JP8152935A | ||||
| JP10215155A | ||||
| JP613857A | ||||
| JP2003133921A |
Attorney, Agent or Firm:
Eiji Saegusa
Kakehi Yuro
Kimio Matsumoto
Kakehi Yuro
Kimio Matsumoto