PURPOSE: To obtain the digital demodulator in which an orthogonal frequency multiplex signal is stably demodulated.
CONSTITUTION: A clock recovery circuit 1610 is made up of a Costas arithmetic operation circuit 1620 and other sections. Registers 1611, 1612 latch only a signal corresponding to a predetermined specific carrier signal for each symbol in signals I', Q' resulting from applying DFT to an orthogonal frequency multiplex signal. Cubic circuits 1621, 1622 cube signals to be received respectively. Multiplier circuits 1623, 1624 respectively multiply the cubed signals I', Q' with the signals I', Q', and a subtractor circuit 1625 detects a phase difference based on the received two signals. The phase difference is converted into a control voltage signal controlling a clock signal generating circuit 162 by a D/A converter circuit 1613 and a low pass filter 1614 and inputted to the clock signal generating circuit 162.
MOMOSHIRO TOSHIHISA
ITO YASU
MIYATO YOSHIKAZU
