Title:
DIGITAL DETECTOR CIRCUIT DEVICE TO RECOVER BIT CLOCK FROM DATA FLOW
Document Type and Number:
Japanese Patent JP3844547
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain a wide capture range by detecting a phase and the length of a pulse signal as digital signals to recover a bit clock from a data flow and using the result of summing and integrating the signals for a tuning signal for a PLL.
SOLUTION: A phase P is fed to a phase detector 1 and the length L of a pulse is fed to a pulse length detector 2. The pulse length detector 2 inputs information representing a side edge of the pulse to be a rising state or a falling state (R/F) and a control signal from a control unit (not shown) in addition to the pulse length L. Output signals from the phase detector 1 and the pulse length detector 2 are added by an adder 4, and its sum is multiplied with (a coefficient -1) in a case. The output signal 6 of an integration device 5 obtained in this way is used for the returning value of a frequency oscillator of a PLL. Thus, a bit lock PLL with an improved capture characteristic is realized.
Inventors:
Friedrich Rominger
Albrecht Rotermel
Heinrich Shemann
Albrecht Rotermel
Heinrich Shemann
Application Number:
JP32246896A
Publication Date:
November 15, 2006
Filing Date:
December 03, 1996
Export Citation:
Assignee:
Deutsche Thomson-Brandt GmbH
International Classes:
H04L7/033; G11B20/14; H03L7/085; H03L7/10; (IPC1-7): H04L7/033; G11B20/14; H03L7/10
Domestic Patent References:
| JP3235270A | ||||
| JP5243991A | ||||
| JP60206339A | ||||
| JP58220226A | ||||
| JP64048268A | ||||
| JP61258534A |
Attorney, Agent or Firm:
Toshio Yano
Toshiomi Yamazaki
Reinhard Einsel
Toshiomi Yamazaki
Reinhard Einsel