Title:
デジタルフィルタ回路およびデジタルフィルタ制御方法
Document Type and Number:
Japanese Patent JP5768819
Kind Code:
B2
Abstract:
[Objective] To provide a digital filter circuit and a digital filter control method which are capable of reducing circuit scale and power consumption for filter processing in a frequency domain such as an overlap FDE method. [Solution] A digital filter circuit according to the present invention includes: an overlap addition means for giving an overlap of M data (M is a positive integer) between the block and the previous block; an FFT processing means for transforming the generated block by FFT processing; a filter computation means for performing filter processing to the transformed block; an IFFT means for transforming the block, which the filter processing was performed to, by IFFT processing; an overlap removal means for removing M units of data from both ends of the transformed block; and a clock generation means for setting the frequency of a filter processing clock signal based on a value of M, wherein the filter processing clock signal drives the data output unit of the overlap addition means, the FFT means, the filter computation means, the IFFT means, and the input unit of the overlap removal means.
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Inventors:
Mitsufumi Shibayama
Application Number:
JP2012549664A
Publication Date:
August 26, 2015
Filing Date:
August 18, 2011
Export Citation:
Assignee:
NEC
International Classes:
H03H17/02; H03H17/00; H04J11/00
Domestic Patent References:
| JP2010124334A | 2010-06-03 | |||
| JPH0823262A | 1996-01-23 | |||
| JP2002108490A | 2002-04-10 |
Attorney, Agent or Firm:
Masahiko Desk
Naoki Shimosaka
Naoki Shimosaka