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Title:
DIGITAL FILTER CIRCUIT
Document Type and Number:
Japanese Patent JPS62262509
Kind Code:
A
Abstract:

PURPOSE: To apply digital filter processing corresponding to number of coefficients generated by three adders, one multiplier and two latch registers by using a coefficient generator generating a determined coefficient storing.

CONSTITUTION: A counter 102 counts from one to ten, and the coefficient generator 103 outputs prescribed coefficients K1, K2∼K7 when the output of the counter 102 is 1∼7 and outputs zero when the output is 8∼10. A picture data inputted from an input terminal is latched by the 1st latch register 101, multiplied with a coefficient generated correspondingly by a multiplier 104 and the result is outputted to the adder 105. The adder 105 and the 2nd latch register 106 constitute an accumulator, which accumulates the result until the counter 102 reaches 7, and is initialized by using a clear signal 107 generated by a clear signal generator 108 when the counter 102 reaches ten. Thus, a picture element data subjected to 7 stage of filters is obtained at an output terminal in the rate of one picture element per ten picture element inputs.


Inventors:
HONDA SHIGE
Application Number:
JP10626386A
Publication Date:
November 14, 1987
Filing Date:
May 09, 1986
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03H17/02; (IPC1-7): H03H17/02
Attorney, Agent or Firm:
Uchihara Shin



 
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