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Title:
DIGITAL FREQUENCY DISCRIMINATOR
Document Type and Number:
Japanese Patent JPS6145975
Kind Code:
A
Abstract:

PURPOSE: To discriminate a frequency with good linearity as long as input frequency is within a discrimination range even if shifting from a reference frequency by using a memory to obtain an error voltage proportional to the frequency difference between the input frequency and rederence discrimination frequency.

CONSTITUTION: The memory 10 is interposed between a latch circuit 8 and a D/A circuit 9; the latch output signal S14 is inputted to the address part of the memory, whose memory output signal S15 is inputted to the circuit 9. When the signal S14 has an upper-limit value, this vaue is inputted to the address part of the memory 10 and an (n)-bit memory output signal S16 is "1" (upper-limit value); when the signal S14 has a value of a slanting part, the signal S16 shows linearity and further when the signal S14 has a lower-limit value, the signal S16 is "0" (lower-limit value). For the purpose, the memory stored with a values for the linearity of the slanting part is used to reduce the capacity of the memory and preform frequency discrimination with good linearity.


Inventors:
MATSUMOTO SHINJI
Application Number:
JP16824884A
Publication Date:
March 06, 1986
Filing Date:
August 11, 1984
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G01R23/10; G05D13/62; H02P29/00; H03K5/19; H03K5/26; (IPC1-7): G01R23/10; G05D13/62; H02P5/00; H03K5/19
Attorney, Agent or Firm:
Toshio Nakao