DIGITAL INFORMATION PROCESSOR

Japanese Patent JP3387837

B2

PROBLEM TO BE SOLVED: To prevent the deterioration of digital information caused by transmission and to make a processor small in size and light in weight as a whole.
SOLUTION: The reproduced signal of an electromagnetic conversion system 14 is inputted to an error correction circuit 34. The error correction circuit 34 corrects an error caused by recording and reproducing in the electromagnetic conversion system 14 based on an error correction code added in an ECC addition circuit 12, and outputs an interpolation flag signal 35 for a correction- disable data. A adding circuit 36 adds an interpolation flag signal 35 to an output of the error correction circuit 34. An ECC adding circuit 38 adds an error correction code to output data of the adding circuit 36, and sends out it to a transmission path 26. In a receiving side, an error correction circuit 40 corrects a transmission error using an error correction code added by the ECC adding circuit 38, and outputs an interpolation flag signal 41 corresponding to the interpolation flag signal 35 and an interpolation flag signal 42 corresponding to correction disable data. The interpolation flag signals 41, 42 are applied to an adding circuit 44. A expanding circuit 30 expands output data of the error correction circuit 40. An interpolation circuit 32 interpolates an output of the expanding circuit 30 conforming to an output of the adding circuit 44.

Shingo Ikeda
Motoichi Kashida

JP32778498A

March 17, 2003

November 18, 1998

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Canon Inc

H04N5/92; G11B20/18; H04B14/04; H04N19/00; H04N19/42; H04N19/46; H04N19/59; H04N19/65; H04N19/70; H04N19/895; (IPC1-7): G11B20/18; H04B14/04; H04N5/92; H04N7/24

JP1296460A

Tsuneo Tanaka

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