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Patent Searching and Data


Title:
DIGITAL LINE TERMINATION CONTROLLER
Document Type and Number:
Japanese Patent JPH03216046
Kind Code:
A
Abstract:

PURPOSE: To avoid the system selection from being unstable due to a secular change or the like by outputting the result of detection of a system selection signal inputted from two systems through an OR circuit.

CONSTITUTION: The coefficient consists of detection circuits 10, 20 and an OR circuit 30, and the detection circuits 10, 20 are provided with counters 11, 12 and inverters 13,14 and each input/output terminal of the inverters 13, 14 connects respectively to an output terminal Q and an enable terminal E of the counters 11, 12. A signal of input frequencies f1, f2 is connected to a reset terminal RST of the counter 11 and a signal of a frequency f3 connects to a clock terminal ck. An output of the inverter 13 connects to the reset terminal RST of the counter 12 and a signal of a frequency f4 connects to the clock terminal ck. Waveforms Q1, Q2 are outputted at an output terminal Q of the counters 11,12. The relation of the frequencies is set as shown in equation I. Thus, the controller consists of the counters, inverters and logic circuits capable of processing large scale integration and the system selection due to a secular change or the like is not unstable.


Inventors:
OKI TAIJI
Application Number:
JP1306490A
Publication Date:
September 24, 1991
Filing Date:
January 22, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04L29/02; (IPC1-7): H04L29/02
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)