PURPOSE: To provide a digital phase locked loop(DPLL) circuit with a small jitter and a wide range of frequency deviation that can respond by using phase control information from a digital loop filter.

CONSTITUTION: Only a random period loop filter part 1 generates a phase control pulse (periodical DPLL control pulse) from an adder 3 at the initial stage, however, a constant period loop filter part 2 also generates the phase control pulse after the lapse of a certain time when frequency deviation is detected. Since the period of the periodical DPLL control pulse in such a case is inversely proportional to the frequency deviation, the periodical DPLL control pulse is generated at shorter intervals in inverse proportion with the frequency deviation with the lapse of time. In such a way, a stationary state is set while approaching the fundamental clock of a subscriber side device (NT) after DPLL control. Meanwhile, when the frequency deviation is small, the period interval of the periodical DPLL control pulse is widened, therefore, phase comparison information can be balanced.