Title:
DIGITAL DELTA/SIGMA MODULATOR
Document Type and Number:
Japanese Patent JP2704480
Kind Code:
B2
Abstract:
PURPOSE: To provide a delta/sigma modulator for a D/A converter through the use of a multiplexed adder constitution.
CONSTITUTION: The delta/sigma modulator has a single adder 60 where one input B is multiplexed by a multiplexer 62. Four shift registers 64, 66, 68 and 70 are connected in series and the output of the adder is connected to the input of the first register 64 and the output of the final register 70 to the other input A of the adder. In a first integration stage, an accumulated value from a previous cycle is added to present data and the output of the integration stage is successively moved through the register at every clock cycle. In the next clock cycle, the multiplexer selects the output of the register 68 previous to the final one and adds it to the output of the final register in a second integration stage. The output of the initial register shows the output of the respective integration stages after the accumulation step and the output is inputted to one of the four shift registers 82, 84, 86 and 88 executing gain scaling.
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Inventors:
Michael El Duffy
Nab Deep Thin Souk
Nab Deep Thin Souk
Application Number:
JP32382892A
Publication Date:
January 26, 1998
Filing Date:
November 10, 1992
Export Citation:
Assignee:
Crystal Semiconductor Corporation
International Classes:
H03M3/02; H03M7/32; (IPC1-7): H03M3/02
Domestic Patent References:
| JP295025A |
Attorney, Agent or Firm:
Koichiro Kato (2 outside)