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Title:
DIGITAL OUTPUT CIRCUIT
Document Type and Number:
Japanese Patent JPH03270629
Kind Code:
A
Abstract:

PURPOSE: To reduce power consumption by a method wherein an output relay is a self retaining type and is controlled sequentially in a accordance with time series employing a shift register, in a digital output circuit outputting digital data employing the relay.

CONSTITUTION: An output circuit is constituted of an oscillating circuit 11, a shift register 12, a control circuit 13, and self-holding relays 141-14n+1. The shift register 12 is provided with (n+2) stages and shifts ready signals by a shift lock from the oscillating circuit 11. The control circuit 13 outputs driving signals sequentially in accordance with time divisions sequentially so as to cope with the parallel input data of (n) bits and the ready signals. The relay necessitates a driving current only upon switching of ON/OFF and effects self- holding by magnetic means after switching. Further, the driving signal is never supplied to more than two relays simultaneously.


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Inventors:
KANDA MAKOTO
Application Number:
JP6867190A
Publication Date:
December 02, 1991
Filing Date:
March 19, 1990
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H02H3/02; (IPC1-7): H02H3/02
Attorney, Agent or Firm:
Tadahiko Ito (2 outside)