PURPOSE: To obtain a phase comparator which is suitably converted into a monolithic IC by having individual comparisons among an inverted line of one side of a reference signal and two inverted lines of a comparison signal and therefore attaining the PLL processing of a digital input data signal having an uneven cycle.

CONSTITUTION: The 1st phase difference detecting circuit 6 detects the phase difference between a rising edge of an input data signal and a rising edge of a PLL clock; while the 2nd phase difference detecting circuit 7 detects the phase difference between a falling edge of the input data signal and a rising edge of the PLL clock. At the same time, a D flip-flop 9 functions as a polarity detecting circuit which detects whether the inverted edge following the input data is rise or fall by latching the input data signal at a falling of the PLL clock. If a PLL clock X1 has a delay to an input data signal X2, a PDout is set at a high level at a time point when the phase difference is finally detected between the output signal X5 of the circuit 6 and the output signal X6 of the circuit 7 with the output X7 of the polarity detecting circuit. Then the oscillation frequency of a VCO is controlled in the phase advance direction of the PLL clock.