Title:
DIGITAL PHASE LOCKED LOOP CIRCUIT
Document Type and Number:
Japanese Patent JPS57181233
Kind Code:
A
Abstract:
A phase-locked loop is implemented using strictly digital techniques. The average frequency of the input signal is first sampled by counting the number of pulses from a clock source which occur during a predetermined number of occurrences of the input signal. Thereafter, the number of pulses counted is divided by the number of cycles of the input signal which occurred during the counting period to determine an average number of pulses per input signal cycle. The number of pulses which occur between successive cycles of the input signal are then counted and compared against the previously determined average. A count which differs from the average indicates a change in phase of the input signal, and after appropriate weighting, is used to update the average to a new average. An output signal is produced when the number of pulses counted during a cycle of the input signal equals the average number of pulses determined to occur between successive cycles of the input signal.
Inventors:
DEBUIDO ROBAATO BOORUDOUIN
NIKORASU SHIRUBUESUTOROFU REMA
NIKORASU SHIRUBUESUTOROFU REMA
Application Number:
JP5615382A
Publication Date:
November 08, 1982
Filing Date:
April 06, 1982
Export Citation:
Assignee:
HONEYWELL INF SYSTEMS
International Classes:
G11B20/14; H03L7/06; H03L7/099; (IPC1-7): H03L7/08
Domestic Patent References:
| JPS5686809A | 1981-07-15 |